Benchmarks for cell-based layout systems
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
An over-cell gate array channel router
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
New algorithm for over-the-cell channel routing using vacant terminals
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A multi-layer channel router with new style of over-the-cell routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A pin permutation algorithm for improving over-the-cell channel routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Over-the-cell channel routing for high performance circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Over-the-cell routers for new cell model
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A unified approach to multilayer over-the-cell routing
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimal algorithms for planar over-the-cell routing in the presence of obstacles
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
On pioneering nanometer-era routing problems
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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When an over-the-cell routing layer is available for standard cell layout, efficient utilization of routing space over the cells can significantly reduce layout area. In this paper, we present three physical models to utilize the area over the cells for routing in standard cell designs. We also present efficient algorithms to choose and to route a planar subset of nets over the cells so that the resulting channel density is reduced as much as possible. For each of the physical models, we show how to arrange inter-cell routing, over-the-cell routing and power/ground busses to achieve valid routing solutions. Each algorithm exploits the particular arrangement in the corresponding physical model and produces provably good results in polynomial time. We tested our algorithms on several industrial standard cell designs. In our tests, this method reduces total channel density as much as 21%.