VIA minimization by layout modification
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Improved channel routing by via minimization and shifting
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
DAC '82 Proceedings of the 19th Design Automation Conference
Efficient Algorithms for Channel Routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Unconstrained Topological Via Minimization Problem for Two-Layer Routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Glitter: A Gridless Variable-Width Channel Router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multi-layer channel router with new style of over-the-cell routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A gridless multi-layer router for standard cell circuits using CTM cells
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Interconnect design methods for memory design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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In this paper, we present a new gridless three layer channel router (MISER) based on an integrated approach to routing and compaction. MISER partitions the input net-list into several sub net-lists called levels and forms a level graph. This level graph is used to guide the routing and compaction process. Compaction is done immediately after each level is routed. Experimental results show that our algorithm usually performs 5-10% better than existing three layer channel routing algorithms.