MISER: an integrated three layer gridless channel router and compactor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Algorithms for permutation channel routing
Integration, the VLSI Journal
Equidistance routing in high-speed VLSI layout design
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Paper: An application of neural networks on channel routing problem
Parallel Computing
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In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.