A parallel bit map processor architecture for DA algorithms
DAC '81 Proceedings of the 18th Design Automation Conference
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Software support for the Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Global wiring on a wire routing machine
DAC '82 Proceedings of the 19th Design Automation Conference
A hardware assisted design rule check architecture
DAC '82 Proceedings of the 19th Design Automation Conference
Cellular image processing techniques for VLSI circuit layout validation and routing
DAC '82 Proceedings of the 19th Design Automation Conference
A Parallel Processing Approach for Logic Module Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A hardware accelerator for maze routing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A Hardware Accelerator for Maze Routing
IEEE Transactions on Computers
Hardware acceleration of gate array layout
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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We develop a systolic design rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design rule check phase of chip design.