An algorithm for design rule checking on a multiprocessor
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Space efficient algorithms for VLSI artwork analysis
DAC '83 Proceedings of the 20th Design Automation Conference
A systolic design rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
Design rule checking and analysis of IC mask designs
DAC '76 Proceedings of the 13th Design Automation Conference
A hardware assisted design rule check architecture
DAC '82 Proceedings of the 19th Design Automation Conference
ARTWORK ANALYSIS TOOL FOR VLSI CIRCUITS
ARTWORK ANALYSIS TOOL FOR VLSI CIRCUITS
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Design rule checking (DRC) is an important step in VLSI design in which the widths and spacings of design features in a VLSI circuit layout are checked against the design rules of a particular fabrication process. In the past, some efforts to build hardware accelerators for DRC have been proposed, but these efforts were hobbled by the fact that it is often impractical to build a different rule-checking ASIC each time design rules or fabrication processes change.In this paper, we propose a configurable hardware approach to DRC. Because the rule-checking is built in configurable hardware, it can garner impressive speedups over software approaches, while retaining the flexibility needed to easily change the rule checker as rules or processes change. Our work proposes an edge-endpoints-based method for performing Manhattan geometry checking; this approach is particularly well-suited to the constraints of configurable hardware. Although design rules do change over time, their intrinsic similarity allows us to propose a general scalable architecture for DRC. We then demonstrate our approach by applying this architecture to a set of design rules for the MOSIS SCN4N_SUB process. The hardware required per rule is quite small; we have implemented several design rule checks within a single Xilinx XC4013 FPGA. Our hardware, implemented on a Pamette board, runs at a clock rate of 33MHz. We also compare the performance of our approach to software methods and demonstrate overall speedups in excess of 25X.