Automatic circuit analysis based on mask information
DAC '76 Proceedings of the 13th Design Automation Conference
Fast algorithm for LSI artwork analysis
25 years of DAC Papers on Twenty-five years of electronic design automation
A layout checking system for large scale integrated circuits
25 years of DAC Papers on Twenty-five years of electronic design automation
An O (N log N) algorithm for boolean mask operations
25 years of DAC Papers on Twenty-five years of electronic design automation
A layout improvement method based on constraint propagation for analog LSI's
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
Efficient Boolean operations on IC masks
DAC '81 Proceedings of the 18th Design Automation Conference
Circuit recognition and verification based on layout information
DAC '81 Proceedings of the 18th Design Automation Conference
Design rule verification based on one dimensional scans
DAC '78 Proceedings of the 15th Design Automation Conference
Design integrity and immunity checking: A new look at layout verification and design rule checking
DAC '80 Proceedings of the 17th Design Automation Conference
An integrated mask artwork analysis system
DAC '80 Proceedings of the 17th Design Automation Conference
A hierarchical bit-map format for the representation of IC mask data
DAC '80 Proceedings of the 17th Design Automation Conference
Automatic circuit analysis based on mask information
DAC '76 Proceedings of the 13th Design Automation Conference
Fast algorithms for LSI artwork analysis
DAC '77 Proceedings of the 14th Design Automation Conference
A layout checking system for large scale integrated circuits
DAC '77 Proceedings of the 14th Design Automation Conference
Programs for verifying circuit connectivity of mos/lsi mask artwork
DAC '82 Proceedings of the 19th Design Automation Conference
LSI layout checking using bipolar device recognition technique
DAC '79 Proceedings of the 16th Design Automation Conference
The design of an efficient data base to support an interactive LSI layout system
DAC '79 Proceedings of the 16th Design Automation Conference
Topological analysis for VLSI circuits
DAC '79 Proceedings of the 16th Design Automation Conference
Circuit recognition and verification from bipolar and MOS layout information
ACM SIGDA Newsletter
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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An efficient method of producing logical combinations of integrated circuit (IC) masks in numerical form leads to a generalized design rule checking program. The union (OR), intersection (AND) and the complements, as well as topological classification and simple geometric operations, are provided through a set of LOGical MASk Checking (LOGMASC) commands, allowing the designer to construct, for the given IC technology, a tailored set of design rule checks. These range from simple tolerance checks to complex analysis of mask geometries based on pattern recognition.