Design rule verification based on one dimensional scans
DAC '78 Proceedings of the 15th Design Automation Conference
Design rule checking and analysis of IC mask designs
DAC '76 Proceedings of the 13th Design Automation Conference
Automatic circuit analysis based on mask information
DAC '76 Proceedings of the 13th Design Automation Conference
The automatic recognition of silicon gate transistor geometries: An LSI design aid program
DAC '76 Proceedings of the 13th Design Automation Conference
An artwork design verification system
DAC '75 Proceedings of the 12th Design Automation Conference
Fast algorithms for LSI artwork analysis
DAC '77 Proceedings of the 14th Design Automation Conference
A layout checking system for large scale integrated circuits
DAC '77 Proceedings of the 14th Design Automation Conference
CRITIC - an integrated circuit design rule checking program
DAC '74 Proceedings of the 11th Design Automation Workshop
MAP: A user-controlled automated Mask Analysis Program
DAC '74 Proceedings of the 11th Design Automation Workshop
Unified Shapes Checker - a checking tool for LSI
DAC '79 Proceedings of the 16th Design Automation Conference
An O (N log N) algorithm for boolean mask operations
25 years of DAC Papers on Twenty-five years of electronic design automation
A circuit comparison system for bipolar linear LSI
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A layout verification system for analog bipolar integrated circuits
DAC '83 Proceedings of the 20th Design Automation Conference
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
PANAMAP-B: A mask verification system for bipolar IC
DAC '81 Proceedings of the 18th Design Automation Conference
Graphics language / one - IBM Corporate-Wide physical design data format
DAC '81 Proceedings of the 18th Design Automation Conference
An integrated mask artwork analysis system
DAC '80 Proceedings of the 17th Design Automation Conference
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Layout errors often result in nonfunctioning devices that still adhere to all layout tolerance rules. Reported here is a method for locating such errors in addition to the tolerance rule checking.