An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Hierarchical circuit extraction with detailed parasitic capacitance
DAC '83 Proceedings of the 20th Design Automation Conference
A hardware assisted design rule check architecture
DAC '82 Proceedings of the 19th Design Automation Conference
A Deterministic finite automaton approach to design rule checking for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
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Current methods for designing VLSI chips do not insure that the chips will perform correctly when manufactured. Because the turn around time on chip fabrication varies from a few weeks to a few months, a scheme other than "try it and see if it works" is needed. Checking of chips by hand simulation and visual inspection of checkplots will not catch all of the errors. In addition, the number of transistors per chip is likely to increase form ten thousand to over a million in the next few years. This increase in complexity precludes any manual verification methods; some better method is needed. A series of programs that use the actual mask descriptors for input are described. These programs perform various levels of checks on the masks, yielding files suitable for simulation. Some of the checks are the usual "design rule" checks of looking for minimum line widths and adequate spacing between the wires. However, there are many more constraints in VLSI circuits than are expressed by the usual design rules. The programs check these constraints using the mask descriptions as input. All of the errors mentioned so far can be classified as syntactic errors; in addition, certain semantic errors are detected. The detection of semantic errors requires various levels of simulation. The input to the simulators is derived from the artwork.