Introduction to VLSI Systems
A parallel bit map processor architecture for DA algorithms
DAC '81 Proceedings of the 18th Design Automation Conference
Fast algorithms for LSI artwork analysis
DAC '77 Proceedings of the 14th Design Automation Conference
CRITIC - an integrated circuit design rule checking program
DAC '74 Proceedings of the 11th Design Automation Workshop
ARTWORK ANALYSIS TOOL FOR VLSI CIRCUITS
ARTWORK ANALYSIS TOOL FOR VLSI CIRCUITS
A hardware accelerator for maze routing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Special purpose architecture for accelerating Bitmap DRC
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A Hardware Accelerator for Maze Routing
IEEE Transactions on Computers
Mask verification on the connection machine
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Tutorial on parallel processing for design automation applications (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
DAC '83 Proceedings of the 20th Design Automation Conference
Space efficient algorithms for VLSI artwork analysis
DAC '83 Proceedings of the 20th Design Automation Conference
A systolic design rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
Parallel processing, special-purpose hardware, and DA applications
CSC-83 Proceedings of the 1983 computer science conference
Incremental analysis of large VLSI Layouts
Integration, the VLSI Journal
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This paper describes an architecture for design rule checking that uses a small amount of special purpose hardware to achieve a significant speed improvement over conventional methods. A fixed grid raster scan algorithm is used that allows checking of 45° angled edges at a modest cost in performance. Operations implemented directly in hardware include width checks, edge condition checks, boolean operations on masks, and shrinking and expansion of masks. Hardware support for rasterization is also provided. Software in a controlling processor handles all geometric data manipulation. This architecture should be able to check a simple set of design rules on a 300 mil square layout in one and one half minutes, if the controlling processor can provide data quickly enough. Layouts have been completed for two of four custom chips used in this architecture, and one has been fabricated and proven functional.