A general purpose multiple way partitioning algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Graph-based techniques to speed up floorplan area optimization
Integration, the VLSI Journal
Network partitioning into tree hierarchies
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A new method for floor planning using topological constraint reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A methodology for fast FPGA floorplanning
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
On Using Tabu Search for Design Automation of VLSI Systems
Journal of Heuristics
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
A New Floorplanning Method for FPGA Architectural Research
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Fast Online Placement for Reconfigurable Computing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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Because the VLSI circuits complexity growth, the trend in design is towards divide-and-conquer schemes, in which circuits are composed of blocks, standard macros or custom macros. From the other side, to allow an implementation of large digital circuits, increased capacity target FPGAs are organized hierarchically. In this paper, we present a hierarchical FPGA floorplanning method which takes into account both the hierarchy of the design and the hierarchy of the target. The method aims at minimization the timing and balancing cost of the floorplan and is based on automatic detection of macro blocks and assigning them to the target FPGA hierarchical zones.