Off-path leakage power aware routing for SRAM-based FPGAs

Authors:
Keheng Huang;Yu Hu;Xiaowei Li;Bo Liu;Hongjin Liu;Jian Gong
Affiliations:
State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences and Graduate University of Chinese Academy of Sciences;State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences;State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences;Beijing Institute of Control Engineering and Science and Technology on Space Intelligent Control Laboratory;Beijing Institute of Control Engineering and Science and Technology on Space Intelligent Control Laboratory;Beijing Institute of Control Engineering and Science and Technology on Space Intelligent Control Laboratory
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

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Abstract

As the feature size and threshold voltage reduce, leakage power dissipation becomes an important concern in SRAM-based FPGAs. This work focuses on reducing the leakage power in routing resources, and more specifically, the leakage power dissipated in the used part of FPGA device, which is known as the active leakage power. We observe that the leakage power in off-path transistors takes up most of the active leakage power in multiplexers that control routing, and strongly depends on Hamming distance between the state of the on-path input and the states of the off-path inputs. Hence, an off-path leakage power aware routing algorithm is proposed to minimize Hamming distance between the state of on-path input and the states of off-path inputs for each multiplexer. Experimental results on MCNC benchmark circuits show that, compared with the baseline VPR technique, the proposed off-path leakage aware routing algorithm can reduce active leakage power in routing resources by 16.79%, and the increment of critical-path delay is only 1.06%.