Techniques and standards for image, video, and audio coding
Techniques and standards for image, video, and audio coding
Low-Complexity Scalable Image Compression
DCC '00 Proceedings of the Conference on Data Compression
A Low Power High Performance Distributed DCT Architecture
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
Journal of VLSI Signal Processing Systems
Proceedings of the conference on Design, automation and test in Europe
An area efficient DCT architecture for MPEG-2 video encoder
IEEE Transactions on Consumer Electronics
New cost-effective VLSI implementation of a 2-D discrete cosine transform and its inverse
IEEE Transactions on Circuits and Systems for Video Technology
VLSI architecture for block-matching motion estimation algorithm
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the Scalable Video Coding Extension of the H.264/AVC Standard
IEEE Transactions on Circuits and Systems for Video Technology
Efficient architectures for 3D HWT using dynamic partial reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
The Journal of Supercomputing
FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration
Journal of Real-Time Image Processing
Design optimization of the quantization and a pipelined 2D-DCT for real-time applications
Multimedia Tools and Applications
Decentralized control for dynamically reconfigurable FPGA systems
Microprocessors & Microsystems
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In this article, we propose field programmable gate array-based scalable architecture for discrete cosine transform (DCT) computation using dynamic partial reconfiguration. Our architecture can achieve quality scalability using dynamic partial reconfiguration. This is important for some critical applications that need continuous hardware servicing. Our scalable architecture has three features. First, the architecture can perform DCT computations for eight different zones, that is, from 1 × 1 DCT to 8× 8 DCT. Second, the architecture can change the configuration of processing elements to trade off the precisions of DCT coefficients with computational complexity. Third, unused PEs for DCT can be used for motion estimation computations. Using dynamic partial reconfiguration with 2.3MB bitstreams, 80 distinct hardware architectures can be implemented. We show the experimental results and comparisons between different configurations using both partial reconfiguration and nonpartial reconfiguration process. The detailed trade-offs among visual quality, power consumption, processing clock cycles, and reconfiguration overhead are analyzed in the article.