Discrete cosine transform: algorithms, advantages, applications
Discrete cosine transform: algorithms, advantages, applications
The JPEG still picture compression standard
Communications of the ACM - Special issue on digital multimedia systems
MPEG: a video compression standard for multimedia applications
Communications of the ACM - Special issue on digital multimedia systems
A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Pipelined Fast 2-D DCT Architecture for JPEG Image Compression
Proceedings of the 14th symposium on Integrated circuits and systems design
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration
ACM Transactions on Embedded Computing Systems (TECS)
On the multiplicative complexity of discrete cosine transforms
IEEE Transactions on Information Theory
An improved scaled DCT architecture
IEEE Transactions on Consumer Electronics
Image quality assessment: from error visibility to structural similarity
IEEE Transactions on Image Processing
IEEE Transactions on Circuits and Systems for Video Technology
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The Discrete Cosine Transform (DCT) is one of the most widely used techniques for image compression. Several algorithms are proposed to implement the DCT-2D. The scaled SDCT algorithm is an optimization of the DCT-1D, which consists in gathering all the multiplications at the end. In this paper, in addition to the hardware implementation on an FPGA, an extended optimization has been performed by merging the multiplications in the quantization block without having an impact on the image quality. A simplified quantization has been performed also to keep higher the performances of the all chain. Tests using MATLAB environment have shown that our proposed approach produces images with nearly the same quality of the ones obtained using the JPEG standard. FPGA-based implementations of this proposed approach is presented and compared to other state of the art techniques. The target is an an Altera Cyclone II FPGA using the Quartus synthesis tool. Results show that our approach outperforms the other ones in terms of processing-speed, used resources and power consumption. A comparison has been done between this architecture and a distributed arithmetic based architecture.