Optimization of the bias current network for accurate on-chip thermal monitoring
Proceedings of the Conference on Design, Automation and Test in Europe
High throughput DA-based DCT with high accuracy error-compensated adder tree
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high performance video transform engine by using space-time scheduling strategy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design optimization of the quantization and a pipelined 2D-DCT for real-time applications
Multimedia Tools and Applications
| Hi-index | 0.00 |
Multimedia applications, and in particular the encoding and decoding of standard image and video formats, are usually a typical target for Systemson- Chip (SoC). The bi-dimensional Discrete Cosine Transformation (2D-DCT) is a commonly used frequency transformation in graphic compression algorithms. Many hardware implementations, adopting disparate algorithms, have been proposed for Field Programmable Gate Arrays (FPGA). These designs focus either on performance or area, and often do not succeed in balancing the two aspects. In this paper, we present a design of a fast 2DDCT hardware accelerator for a FPGA-based SoC. This accelerator makes use of a single seven stages 1D-DCT pipeline able to alternate computation for the even and odd coefficients in every cycle. In addition, it uses special memories to perform the transpose operations. Our hardware takes 80 clock cycles at 107MHz to generate a complete 8x8 2D DCT, from the writing of the first input sample to the reading of the last result (including the overhead of the interface logic). We show that this architecture provides optimal performance/ area ratio with respect to several alternative designs.