VLSI architecture for block-matching motion estimation algorithm

Authors:
C. -H. Hsieh;T. -P. Lin
Affiliations:
Dept. of Electr. Eng., Chung Cheng Univ., Taoyuan;-
Venue:
IEEE Transactions on Circuits and Systems for Video Technology
Year:
1992

Citing 0
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Expert system based parallel multi-1D block matching algorithm with implementation for motion estimation

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Abstract

The block-matching motion estimation is the most popular method for motion-compensated coding of image sequence. A VLSI architecture for implementing a full-search block-matching algorithm is presented. Based on a systolic array processor and shift register arrays with programmable length, the proposed architecture has the following advantages: it allows serial data input to save the pin counts but performs parallel processing; it is flexible in adaptation to the dimensional change of the search area via simple control; it can operate in real time for videoconference applications; and it is simple and modular in design, and thus is suitable for VLSI implementation