Recursive 3-D Road and Relative Ego-State Recognition
IEEE Transactions on Pattern Analysis and Machine Intelligence - Special issue on interpretation of 3-D scenes—part II
Selected Papers from the International Workshop on Sensor Based Intelligent Robots
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A Coprocessor for Accelerating Visual Information Processing
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A video segmentation algorithm for hierarchical object representations and its implementation
IEEE Transactions on Circuits and Systems for Video Technology
System-platforms-based SystemC TLM design of image processing chains for embedded applications
EURASIP Journal on Embedded Systems
Proceedings of the conference on Design, automation and test in Europe
A Networked, Lightweight and Partially Reconfigurable Platform
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems
IWSEC '08 Proceedings of the 3rd International Workshop on Security: Advances in Information and Computer Security
Ultra-Fast Downloading of Partial Bitstreams through Ethernet
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration
ACM Transactions on Embedded Computing Systems (TECS)
Efficient architectures for 3D HWT using dynamic partial reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
Demonstration of an in-band reconfiguration data distribution and network node reconfiguration
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Signal Processing Systems
Functionally verifying state saving and restoration in dynamically reconfigurable systems
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
The Journal of Supercomputing
An approach for redundancy in FlexRay networks using FPGA partial reconfiguration
Proceedings of the Conference on Design, Automation and Test in Europe
Simulation-based functional verification of dynamically reconfigurable systems
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper we show a reconfigurable hardware architecture for the acceleration of video-based driver assistance applications in future automotive systems. The concept is based on a separation of pixel-level operations and high level application code. Pixel-level operations are accelerated by coprocessors, whereas high level application code is implemented fully programmable on standard PowerPC CPU cores to allow flexibility for new algorithms. In addition, the application code is able to dynamically reconfigure the coprocessors available on the system, allowing for a much larger set of hardware accelerated functionality than would normally fit onto a device. This process makes use of the partial dynamic reconfiguration capabilities of Xilinx Virtex FPGAs.