Energy-aware adaptation for mobile applications
Proceedings of the seventeenth ACM symposium on Operating systems principles
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Tiling optimizations for 3D scientific computations
Proceedings of the 2000 ACM/IEEE conference on Supercomputing
Real-time dynamic voltage scaling for low-power embedded operating systems
SOSP '01 Proceedings of the eighteenth ACM symposium on Operating systems principles
Influence of compiler optimizations on system power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
The Effect of Compiler Optimizations on Pentium 4 Power Consumption
INTERACT '03 Proceedings of the Seventh Workshop on Interaction between Compilers and Computer Architectures
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization
Proceedings of the conference on Design, automation and test in Europe
A Power-Aware Run-Time System for High-Performance Computing
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
Model-guided empirical optimization for memory hierarchy
Model-guided empirical optimization for memory hierarchy
Just-in-time dynamic voltage scaling: Exploiting inter-node slack to save energy in MPI programs
Journal of Parallel and Distributed Computing
Prediction-based power estimation and scheduling for CMPs
Proceedings of the 23rd international conference on Supercomputing
A scalable auto-tuning framework for compiler optimization
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
PowerPack: Energy Profiling and Analysis of High-Performance Systems and Applications
IEEE Transactions on Parallel and Distributed Systems
Profile-based optimization of power performance by using dynamic voltage scaling on a PC cluster
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Automated empirical tuning of scientific codes for performance and power consumption
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Reducing energy usage with memory and computation-aware dynamic frequency scaling
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part I
Fine-Grained Energy Consumption Characterization and Modeling
HPCMP-UGC '10 Proceedings of the 2010 DoD High Performance Computing Modernization Program Users Group Conference
Compiling for power with ScalaPipe
Journal of Systems Architecture: the EUROMICRO Journal
OpenMP and MPI application energy measurement variation
E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
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The power wall has become a dominant impeding factor in the realm of exascale system design. It is therefore important to understand how to most effectively create software to minimize its power usage while maintaining satisfactory levels of performance. This work uses existing software and hardware facilities to tune applications to minimize for several combinations of power and performance. The tuning is done with respect to software level performance-related tunables and for processor clock frequency. These tunable parameters are explored via an offline search to find the parameter combinations that are optimal with respect to performance (or delay, D), energy (E), energy×delay (E×D) and energy×delay×delay (E×D2). These searches are employed on a parallel application that solves Poisson's equation using stencils. We show that the parameter configuration that minimizes energy consumption can save, on average, 5.4% energy with a performance loss of 4% when compared to the configuration that minimizes runtime.