Profile-based optimization of power performance by using dynamic voltage scaling on a PC cluster

  • Authors:
  • Yoshihiko Hotta;Mitsuhisa Sato;Hideaki Kimura;Satoshi Matsuoka;Taisuke Boku;Daisuke Takahashi

  • Affiliations:
  • Graduate School of Systems & Information Engineering, University of Tsukuba;Graduate School of Systems & Information Engineering, University of Tsukuba;Graduate School of Systems & Information Engineering, University of Tsukuba;Tokyo Institute of Technology;Graduate School of Systems & Information Engineering, University of Tsukuba;Graduate School of Systems & Information Engineering, University of Tsukuba

  • Venue:
  • IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
  • Year:
  • 2006

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Abstract

Currently, several of the high performance processors used in a PC cluster have a DVS (Dynamic Voltage Scaling) architecture that can dynamically scale processor voltage and frequency. Adaptive scheduling of the voltage and frequency enables us to reduce power dissipation without a performance slowdown during communication and memory access. In this paper, we propose a method of profiledbased power-performance optimization by DVS scheduling in a high-performance PC cluster. We divide the program execution into several regions and select the best gear for power efficiency. Selecting the best gear is not straightforward since the overhead of DVS transition is not free. We propose an optimization algorithm to select a gear using the execution and power profile by taking the transition overhead into account. We have built and designed a power-profiling system, PowerWatch. With this system we examined the effectiveness of our optimization algorithm on two types of power-scalable clusters (Crusoe and Turion). According to the results of benchmark tests, we achieved almost 40% reduction in terms of EDP (energy-delay product) without performance impact (less than 5%) compared to results using the standard clock frequency.