Modifications of the Nelder-Mead simplex method for stochastic simulation response optimization
WSC '91 Proceedings of the 23rd conference on Winter simulation
Automatic performance setting for dynamic voltage scaling
Proceedings of the 7th annual international conference on Mobile computing and networking
Journal of Global Optimization
Making a Case for Efficient Supercomputing
Queue - Power Management
Power and Energy Profiling of Scientific Applications on Distributed Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
A Power-Aware Run-Time System for High-Performance Computing
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
The 48-core SCC Processor: the Programmer's View
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Profile-based optimization of power performance by using dynamic voltage scaling on a PC cluster
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Prefetching in Embedded Mobile Systems Can Be Energy-Efficient
IEEE Computer Architecture Letters
Memory-side acceleration for XML parsing
NPC'11 Proceedings of the 8th IFIP international conference on Network and parallel computing
Achieving middleware execution efficiency: hardware-assisted garbage collection operations
The Journal of Supercomputing
IEEE Transactions on Education
Packer: Parallel Garbage Collection Based on Virtual Spaces
IEEE Transactions on Computers
Proceedings of International Workshop on Adaptive Self-tuning Computing Systems
| Hi-index | 0.00 |
With the technology advancement, we are quickly progressing towards the many-core era. Corresponding to this shift, techniques on how we program such chip are beginning to change. The Single-Chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. When programmer is given direct control over the frequency and voltage of the cores, ideally we want to identify the phases of the program based on their computation intensity and associate frequency and voltage configuration correspondingly. In order to achieve power and energy saving in this way, however, we need to search through the entire domain of various voltage and frequency combinations supported by the chip, which is a daunting task. In this study, we propose to employ two popular optimization algorithms, i.e., Differential Evolution and Nelder-Mead Simplex, to help identifying the best configuration corresponding to various metrics, i.e., execution time, power, energy, and energy-delay product (EDP). Our experimental evaluation shows that, with a large search space of possible combinations, we can identify the configuration that provides the best result for each specific metric, which aids the tuning for individual phases.