Performance and yield enhancement of FPGAs with within-die variation using multiple configurations

Authors:
Yohei Matsumoto;Masakazu Hioki;Takashi Kawanami;Toshiyuki Tsutsumi;Tadashi Nakagawa;Toshihiro Sekigawa;Hanpei Koike
Affiliations:
National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan and CREST, Japan Science and Technology Agency;National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan and CREST, Japan Science and Technology Agency;National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan and CREST, Japan Science and Technology Agency;National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan, CREST, Japan Science and Technology Agency and Meiji University, Kanagawa, Japan;National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan;National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan;National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan and CREST, Japan Science and Technology Agency
Venue:
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Year:
2007

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Abstract

A new method for improving the timing yield of field-programmable gate array (FPGA) devices affected by random within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations such that the critical paths do not share same circuit resources on the FPGA, both the average critical path delay and its standard deviation are reduced substantially under conditions of large random variation. Large within-die variations of device parameters such as transistor threshold voltage are anticipated in future semiconductor technologies, resulting in degradation of parametric yields. Comparing to the previous approach which compensates for such within-die variation by designing circuit placement for each chip using variation information measured before, our method does not require the measurement of process variations and execution of design tools for each chip. The average critical path delay is reduced by up to 5% assuming 30% (σ/μ) variation in threshold voltage, with a corresponding 50% decrease in standard deviation.