VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Structured ASIC, evolution or revolution?
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance
Proceedings of the 50th Annual Design Automation Conference
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The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the development of Design-Specific FPGAs. These parts offer cost reductions by limiting manufacturing tests and improving the number of working devices in a wafer. This paper addresses the issue of yield enhancement in Design-Specific FPGAs. In this paper, an analytical model predicting the probability of mapping a specific design onto potentially defective FPGAs is developed. When combined with existing yield modelling techniques, a quantitative measure of the potential yield improvements of the Design-Specific FPGA approach is reported for current and future technology nodes. It is found that this approach, while beneficial with current manufacturing technology, may not be suitable for 22nm technology or beyond.