Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance

Authors:
Jason Cong;Bingjun Xiao
Affiliations:
University of California, Los Angeles and California Nano-System Institute;University of California, Los Angeles
Venue:
Proceedings of the 50th Annual Design Automation Conference
Year:
2013

Citing 13
Cited 0

PathFinder: a negotiation-based performance-driven router for FPGAs

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Efficiently supporting fault-tolerance in FPGAs

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs

Architecture and CAD for Deep-Submicron FPGAs
Column-Based Precompiled Configuration Techniques for FPGA

FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Yield enhancements of design-specific FPGAs

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Fault tolerant placement and defect reconfiguration for nano-FPGAs

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Efficient FPGAs using nanoelectromechanical relays

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder

Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Choose-your-own-adventure routing: Lightweight load-time defect avoidance

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously

Proceedings of the International Conference on Computer-Aided Design
Limit study of energy & delay benefits of component-specific routing

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Performance Benefits of Monolithically Stacked 3-D FPGA

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This work focuses on defect tolerance for nanodevice-based programmable interconnects of FPGAs. First, we show that the stuck-closed defects of nanodevices have a much higher impact than the stuck-open defects. Instead of simply avoiding the stuck-closed defects, we use them by treating them as shorting constraints in the routing. We develop a scalable algorithm to perform timing-driven routing under these extra constraints. We also enhance the placement algorithm to recover logic blocks which become virtually unusable due to shorted pins. Simulation results show that at the up-to-date level of nanodevice defects (108--1011x higher than CMOS), compared to the simple avoidance method, our approach reduces the degradation of resource usage by 87%, improves the routability by 37%, and reduce the degradation of circuit performance by 36%, at a negligible overhead of tool runtime.