Circuit design of routing switches
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Reconfigurable architectures for general-purpose computing
Reconfigurable architectures for general-purpose computing
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Area and delay trade-offs in the circuit and architecture design of FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
rFGA: CMOS-nano hybrid FPGA using RRAM components
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
Efficient FPGAs using nanoelectromechanical relays
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Customizable Domain-Specific Computing
IEEE Design & Test
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Power modeling and characteristics of field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance Benefits of Monolithically Stacked 3-D FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
A non-volatile reconfigurable offloader for wireless sensor nodes
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance
Proceedings of the 50th Annual Design Automation Conference
Nano-electro-mechanical relays for FPGA routing: experimental demonstration and a design technique
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration (mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D die-stacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional FPGAs, the positions of inserted buffers in mrFPGA are optimized on demand. A complete CAD flow is provided for mrFPGA, with an advanced P&R tool named mrVPR that was developed for mrFPGA. The tool can deal with the novel routing structure of mrFPGA, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrFPGA based on the 20 largest MCNC benchmark circuits. Results show that mrFPGA achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrFPGA.