Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications
Proceedings of the 44th annual Design Automation Conference
Low power FPGA design using hybrid CMOS-NEMS approach
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Area and delay trade-offs in the circuit and architecture design of FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
FPCNA: a field programmable carbon nanotube array
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Integrated circuit design with NEM relays
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage
Proceedings of the 2009 International Conference on Computer-Aided Design
Efficient FPGAs using nanoelectromechanical relays
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
mrFPGA: A novel FPGA architecture with memristor-based reconfiguration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Architecture and performance evaluation of 3D CMOS-NEM FPGA
Proceedings of the System Level Interconnect Prediction Workshop
A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA
IEEE Transactions on Nanotechnology
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Nano-Electro-Mechanical (NEM) relays are excellent candidates for programmable routing in Field Programmable Gate Arrays (FPGAs). FPGAs that combine CMOS circuits with NEM relays are referred to as CMOS-NEM FPGAs. In this paper, we experimentally demonstrate, for the first time, correct functional operation of NEM relays as programmable routing switches in FPGAs, and their programmability by utilizing hysteresis properties of NEM relays. In addition, we present a technique that utilizes electrical properties of NEM relays and selectively removes or downsizes routing buffers for designing energy-efficient CMOS-NEM FPGAs. Simulation results indicate that such CMOS-NEM FPGAs can achieve 10-fold reduction in leakage power, 2-fold reduction in dynamic power, and 2-fold reduction in area, simultaneously, without application speed penalty when compared to a 22nm CMOS-only FPGA.