Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage

Authors:
Soogine Chong;Kerem Akarvardar;Roozbeh Parsa;Jun-Bo Yoon;Roger T. Howe;Subhasish Mitra;H.-S. Philip Wong
Affiliations:
Stanford University, Stanford, CA;Stanford University, Stanford, CA;Stanford University, Stanford, CA;KAIST, Yuseong-gu, Daejon, Korea;Stanford University, Stanford, CA;Stanford University, Stanford, CA;Stanford University, Stanford, CA
Venue:
Proceedings of the 2009 International Conference on Computer-Aided Design
Year:
2009

Citing 6
Cited 6

RF MEMS: Theory, Design, and Technology

RF MEMS: Theory, Design, and Technology
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation

Proceedings of the 2003 international symposium on Low power electronics and design
Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications

Proceedings of the 44th annual Design Automation Conference
Process variation tolerant SRAM array for ultra low voltage applications

Proceedings of the 45th annual Design Automation Conference
Integrated circuit design with NEM relays

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
High-performance SRAM in nanoscale CMOS: Design challenges and techniques

MTDT '07 Proceedings of the 2007 IEEE International Workshop on Memory Technology, Design and Testing

Efficient FPGAs using nanoelectromechanical relays

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS

Proceedings of the 47th Design Automation Conference
A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop

NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
NEMS based thermal management for 3D many-core system

NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Nano-electro-mechanical relays for FPGA routing: experimental demonstration and a design technique

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present a hybrid nanoelectromechanical (NEM)/CMOS static random access memory (SRAM) cell, in which the two pull-down transistors of a conventional CMOS six transistor (6T) SRAM cell are replaced with NEM relays. This SRAM cell utilizes the infinite subthreshold slope and hysteretic properties of NEM relays to dramatically increase the cell stability compared to the conventional CMOS 6T SRAM cells. It also utilizes the zero off-state leakage of NEM relays to significantly decrease static power dissipation. The structure is designed so that the relatively long mechanical delay of the NEM relays does not result in performance degradation. Circuit simulations are performed using a VerilogA model of a NEM relay. Compared to a 65nm CMOS 6T SRAM cell, when 10nm-gap NEM relays (pull-in voltage = 0.8V, pull-out voltage = 0.2V, on resistance = 1kΩ) are integrated, hold and read static noise margin (SNM) improve by ~110% and ~250%, respectively. In addition, static power dissipation decreases by ~85%. The write delay decreases by ~60%, while read delay decreases by ~10%. The advantages in SNM and static power dissipation are expected to increase with scaling.