High-performance SRAM in nanoscale CMOS: Design challenges and techniques

• Authors: Ching-Te Chuang;Saibal Mukhopadhyay; Jae-Joon Kim; Keunwoo Kim;Rahul Rao
• Venue: MTDT '07 Proceedings of the 2007 IEEE International Workshop on Memory Technology, Design and Testing
• Year: 2007

This paper reviews the design challenges and techniques of high-performance SRAM in the “End of Scaling” nanoscale CMOS technologies. The impacts of technology scaling, such as signal loss due to leakage, degradation of noise margin due to VT scatter caused by process variations and random dopant fluctuation, and long term reliability degradation such as NBTI, are addressed. Design directions and leakage/variation/degradation tolerant SRAM circuit techniques to mitigate various performance and reliability constraints in conventional planar CMOS technology are discussed. Examples are given and merits discussed for cell isolation and strength preservation, thin cell layout, bit-line and word-line leakage mitigation, migration to large signal read-out, unclamped bit-line, dual-supply, dynamic Read/Write supply, floating power-line, header/footer power-gating structures, Read- and Write-assist circuits, leakage/variation detection and compensation techniques, word-line and bit-line pulsing schemes, gate leakage tolerant design, and NBTI tolerant design. Alternative cell structures, such as asymmetrical SRAM, 7T, and 8T SRAMs, which decouple the cell storage node from the Read-disturb and half-select disturb to improve the SNM are discussed. Finally, some design issues and opportunities in emerging technologies such as FD/SOI and multi-gate FinFET are illustrated.