Parametric yield analysis and optimization in leakage dominated technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-performance SRAM in nanoscale CMOS: Design challenges and techniques
MTDT '07 Proceedings of the 2007 IEEE International Workshop on Memory Technology, Design and Testing
IBM Journal of Research and Development
Power optimization methodology for the IBM POWER7 microprocessor
IBM Journal of Research and Development
Adaptive energy-management features of the IBM POWER 7 chip
IBM Journal of Research and Development
Design methodology for the IBM POWER7 microprocessor
IBM Journal of Research and Development
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The IBM POWER7+™ microprocessor is the next-generation IBM POWER® processor implemented in IBM's 32-nm silicon-on-insulator process. In addition to enhancing the chip functionality, implementing core-level and chiplet-level power gating and significantly increasing the size of the on-chip cache, the chip achieves a frequency boost of 15% to 25% compared with its predecessor at the same power. To achieve these challenging goals and deliver a serviceable power-frequency limited yield (PFLY), the IBM team made significant innovations in the post-silicon hardware-tuning methodology to counteract the inherent process variability and developed new PFLY models that account for several sources of variability in power and frequency. The paper describes the new methodology and the models, provides analysis of the sources of variability and their impact on power and frequency, and describes the work done to achieve correlation between the models and hardware measurements.