Ultra-low power digital subthreshold logic circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
Proceedings of the IEEE International Test Conference
Review and future prospects of low-voltage RAM circuits
IBM Journal of Research and Development
A Feasibility Study of Subthreshold SRAM Across Technology Generations
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM
Integration, the VLSI Journal
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Independently-controlled-gate FinFET schmitt trigger sub-threshold SRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this work, we propose a Schmitt Trigger (ST) based differential sensing SRAM bitcell that can operate at ultra-low supply voltage. The proposed Schmitt Trigger SRAM cell addresses the fundamental conflicting design requirement of read versus write operation of a conventional 6T cell. Schmitt Trigger operation gives better read-stability and as well as better writeability compared to the standard 6T cell. The proposed ST bitcell incorporates a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes. Measurements on 10 test-chips fabricated in 130nm technology show that the proposed Schmitt Trigger bitcell gives 58% higher read Static Noise Margin (SNM), 2X higher writetrip-point and 120mV lower read Vmin compared to the conventional 6T cell. The ST SRAM array is operational at 150mV of supply voltage.