Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Process variation tolerant SRAM array for ultra low voltage applications
Proceedings of the 45th annual Design Automation Conference
Impact of LER and Random Dopant Fluctuations on FinFET Matching Performance
IEEE Transactions on Nanotechnology
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In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-gate 6 T cell, the proposed IG_ST SRAM cells demonstrate 1.81× and 2.11× higher nominal RSNM at Vcs = 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger subthreshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations (Leff, EOT, Wfin, and Hfin) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of µ/σ ratio.