New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
A low leakage 9t sram cell for ultra-low power operation
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Process variation tolerant SRAM array for ultra low voltage applications
Proceedings of the 45th annual Design Automation Conference
Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO
Microelectronics Journal
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM
Integration, the VLSI Journal
Hi-index | 0.00 |
In this paper, a novel design flow is presented for power minimization of nano-CMOS SRAM (static random access memory) circuits, while maintaining their performance. A 32nm high-K/metalgate SRAM is used as an example circuit. The baseline SRAM circuit is subjected to power minimization using a dual-VTh assignment based on a novel Design of Experiments-Integer Linear Programming (DOE-ILP) approach. However, this leads to a 15% reduction in the Static Noise Margin (SNM) of the SRAM, which is an indicator of the stability degradation of the SRAM. This reduction in the SNM is then overcome using a conjugate gradient optimization, while maintaining the minimum power consumption. The final SRAM design shows 86% reduction in power (including leakage) consumption and 8% increase in the SNM compared to the baseline design. The variability analysis of the optimized cell is carried out considering the variability effect in 12 parameters to study the robustness of the optimal SRAM circuit. An 8 x 8 array is constructed to show the feasibility of the proposed SRAM.