DRG-cache: a data retention gated-ground cache for low power
Proceedings of the 39th annual Design Automation Conference
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Techniques for Multicore Thermal Management: Classification and New Exploration
Proceedings of the 33rd annual international symposium on Computer Architecture
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Low power FPGA design using hybrid CMOS-NEMS approach
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proactive temperature management in MPSoCs
Proceedings of the 13th international symposium on Low power electronics and design
Accurate energy breakeven time estimation for run-time power gating
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Integrated circuit design with NEM relays
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Temperature-constrained power control for chip multiprocessors with online model estimation
Proceedings of the 36th annual international symposium on Computer architecture
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage
Proceedings of the 2009 International Conference on Computer-Aided Design
Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-Level Dynamic Thermal Management for High-Performance Microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Leakage power has become the dominant factor to the total power consumption when technology scales down to nano-region. Moreover, due to the exponential relationship between leakage power and temperature, positive feedback loop can cause thermal-runaway hazard. This poses a significant barrier for 3D integration of multi-cache-core processor, which has high I/O bandwidth but also has high leakage-power density and long heat-removal path. Nano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices to solve the thermal-runaway problem due to their zero leakage current and infinite sub-threshold slope. In order to have a proper control of thermal-runaway hazard for many-core system, this paper studies hybrid CMOS-NEMS designs of thermal buffer and power gating to reduce leakage power and thermal-runaway at thermal-time-constant scale. Experimental results show that our proposed NEMS based thermal management can effectively prevent the thermal-runaway in 3D multi-cache-core processor.