Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Exploring technology alternatives for nano-scale FPGA interconnects
Proceedings of the 42nd annual Design Automation Conference
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Performance analysis of carbon nanotube interconnects for VLSI applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Proceedings of the 43rd annual Design Automation Conference
A new hybrid FPGA with nanoscale clusters and CMOS routing
Proceedings of the 43rd annual Design Automation Conference
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Variation-aware routing for FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Low power FPGA design using hybrid CMOS-NEMS approach
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Single-walled carbon nanotube electronics
IEEE Transactions on Nanotechnology
A circuit-compatible model of ballistic carbon nanotube field-effect transistors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Read-out schemes for a CNTFET-based crossbar memory
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Monolithically stackable hybrid FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
Reconfigurable circuit design with nanomaterials
Proceedings of the Conference on Design, Automation and Test in Europe
Design investigation of nanoelectronic circuits using crossbar-based nanoarchitectures
Microelectronics Journal
Nano-electro-mechanical relays for FPGA routing: experimental demonstration and a design technique
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Carbon nanotubes (CNTs), with their unique electronic properties, are promising materials for building nanoscale circuits. In this paper, we present a new CNT-based FPGA architecture known as FPCNA. We define novel CNT and nanoswitch based components and characterize these components considering nano-specific process variations, including the variation caused by the random mixture of metallic and semiconducting CNTs. To evaluate the architecture, we develop a variation-aware physical-design flow which can handle both Gaussian and non-Gaussian random variables using variation-aware placement and routing. When FPCNA is evaluated with this CAD flow, we see a 2.67× performance gain over a baseline CMOS FPGA at the same technology node (at a 95% performance yield). In addition, FPCNA offers a 4.5× footprint reduction compared to the baseline FPGA. These results demonstrate the potential of using CNTs and nanoswitches to build high performance FPGA circuits.