Proceedings of the International Conference on Computer-Aided Design
Nano-electro-mechanical relays for FPGA routing: experimental demonstration and a design technique
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Energy efficiency and idle power consumption are becoming important parameters in the design of embedded systems that are realized with nanometer-scale CMOS devices. In nanometer-scale CMOS, Excessive quiescent power dissipation can lead to excessive heat generation and reliability issues. To address energy efficiency and idle power consumption, we present a novel Complementary Nano-Electro-Mechanical (CNEM) switch that we manufactured which operates with virtually zero leakage current, has 1 to 2 Volts operation voltage, $$ 1 GHZ fundamental resonant frequency, and nanometer-scale footprint. These CNEM switches can be “dropped” in and hybridized with CMOS at the metallization or device levels to manage leakage current and power. In this paper, we present a hybrid CMOS/CNEMS FPGA. The hybrid FPGA is based on using the CNEM switching device as a replacement of CMOS devices in the switch and connection block components found in FPGA architectures. We analyzed the impact of the CNEM substitution on power and delay using VPR and the MCNC benchmark circuits. We present experimental results showing an average 98\%, 85\%, 71\%, and 99.99\% reduction in critical path delay, routing energy, total energy, leakage power when comparisons are made between FPGA design using pure CMOS (180nm technology and hybrid CNEMS and CMOS (180nm) technology.