The design of a low energy FPGA
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Leakage control in FPGA routing fabric
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low power FPGA design using hybrid CMOS-NEMS approach
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Efficient FPGAs using nanoelectromechanical relays
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
FPGA based on integration of carbon nanorelays and CMOS devices
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Circuits and architectures for field programmable gate array with configurable supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we discuss a new type of NEMS switches that can be configured to implement any 2-input logic gates (AND, OR, NAND, NOR, XOR, XNOR, NOT) in a single device structure. These devices can be used to implement FPGA where a four-input CLB requires only nine NEMS switches and at most two mechanical delays per computation. In contrast, CMOS CLBs require 150 traditional switches. By reducing the number of devices, our approach improves yield, reproducibility, speed, power and simplifies implementation.