Ultra-low power NEMS FPGA

Authors:
Sijing Han;Vijay Sirigiri;Daniel G. Saab;Massood Tabib-Azar
Affiliations:
Case Western Reserve University, Cleveland, Ohio;Case Western Reserve University, Cleveland, Ohio;Case Western Reserve University, Cleveland, Ohio;University of Utah, Salt Lake City, Utah
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2012

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Abstract

In this paper, we discuss a new type of NEMS switches that can be configured to implement any 2-input logic gates (AND, OR, NAND, NOR, XOR, XNOR, NOT) in a single device structure. These devices can be used to implement FPGA where a four-input CLB requires only nine NEMS switches and at most two mechanical delays per computation. In contrast, CMOS CLBs require 150 traditional switches. By reducing the number of devices, our approach improves yield, reproducibility, speed, power and simplifies implementation.