Circuit design of routing switches
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Low power FPGA design using hybrid CMOS-NEMS approach
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
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In this paper, a novel reconfigurable architecture, cFPGA (CMOS-Nanorelay FPGA) is developed by integrating carbon nanorelays and CMOS devices to function as FPGA components. cFPGA is a highly efficient architecture, providing 2X density and standby power improvement along with 30% dynamic power reduction as compared to the CMOS FPGA circuits. This performance improvement is achieved by using 2T1N structures as routing switches: Two CMOS transistors (2T): one for programming purpose and the other for signal transmission; one nanorelay (1N): the switching element. These 2T1N structures do not have nanorelays in the signal path, thereby eliminating the large quantum resistance in the path. This is a significant improvement over the conventional CMOS-nanorelay hybrid FPGA circuits. The proposed cFPGA is implemented using vertical carbon nanotubes which are relatively easier to fabricate as compared with horizontal nanotubes.