CMOL: Second life for silicon?
Microelectronics Journal
High-performance carbon nanotube field-effect transistor with tunable polarities
IEEE Transactions on Nanotechnology
Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
mrFPGA: A novel FPGA architecture with memristor-based reconfiguration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Ultra-fine grain FPGAs: A granularity study
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
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This paper describes an interconnection scheme and its associated mapping method, used to program complex functions onto reconfigurable architectures, based on nanoscale logic cells. To interconnect such fine-grain logic cells, classical techniques are not suitable because of a large overhead. Therefore, we propose the use of static and incomplete interconnection topologies. We also propose a method to map functions onto such architectures. To evaluate the 4 different proposed topologies, we test mapping efficiency, performances and fault tolerance. The analyses show that this approach could improve the scalability of traditional EPGAs by a factor of 8.