A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Self-Measurement of Combinatorial Circuit Delays in FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A Low Overhead On-Chip Path Delay Measurement Circuit
ATS '09 Proceedings of the 2009 Asian Test Symposium
A Delay Measurement Technique Using Signature Registers
ATS '09 Proceedings of the 2009 Asian Test Symposium
Degradation in FPGAs: measurement and modelling
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Dynamic voltage & frequency scaling with online slack measurement
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
| Hi-index | 0.00 |
The ability to measure delay of arbitrary circuits on FPGA offers many opportunities for on-chip characterisation and optimisation. This paper describes an improved delay measurement method by monitoring the transition probability at the output nodes as the operating frequency is swept. The new method uses optimised test vector generation to improve the accuracy of the test method. It is effectively demonstrated on a 4th order IIR filter circuit implemented on an Altera Cyclone III FPGA.