Performance verification of high-performance ASICs using at-speed structural test
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Variability driven gate sizing for binning yield optimization
Proceedings of the 43rd annual Design Automation Conference
Yield-Aware Cache Architectures
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Evaluating the effects of cache redundancy on profit
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
System-level process variability analysis and mitigation for 3D MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Improved delay measurement method in FPGA based on transition probability
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spectrum. Consequently, speed binning of the high performance VLSI chips is essential and it costs significant amount of test application time. Further, the knowledge of the actual delay in the critical path of the circuit enables efficient use of typical low power methodologies e.g., voltage scaling, adaptive body biasing etc. In this paper, we have proposed a novel on-chip, low overhead and process tolerant delay measurement circuit which can estimate the critical path delay in a single clock period. This has the advantage of efficient on-chip speed binning.