Improved delay measurement method in FPGA based on transition probability
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
The survivability of design-specific spare placement in FPGA architectures with high defect rates
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamic voltage & frequency scaling with online slack measurement
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Progress in VLSI technology is driven by increasing circuit density through process scaling, but with shrinking geometry comes an increasing threat to reliability. FPGAs are uniquely placed to tackle degradation and faults due to their regular structure and ability to reconfigure, giving them the potential to implement system-level reliability enhancements. To assess the scale of the challenge, a method for measuring and monitoring degradation in an FPGA was developed and used to conduct an accelerated life test on a modern device. This revealed a clear, gradual degradation in timing performance that matches the expected effects of Negative-Bias Temperature Instability and Hot Carrier Injection, two of the most important VLSI degradation mechanisms. Further insight into ageing phenomena was gained using modelling -- showing how degradation in a typical LUT would be affected by different usage conditions, and predicting in detail the effects on circuit behaviour.