GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction

Authors:
Benjamin Gojman;Sirisha Nalmela;Nikil Mehta;Nicholas Howarth;André DeHon
Affiliations:
University of Pennsylvania, Philadelphia, PA, USA;Juniper Networks, Westford, MA, USA;California Institute of Technology, Pasadena, CA, USA;University of Pennsylvania, Philadelphia, PA, USA;University of Pennsylvania, Philadelphia, PA, USA
Venue:
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Year:
2013

Citing 8
Cited 0

PathFinder: a negotiation-based performance-driven router for FPGAs

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Defect tolerance on the Teramac custom computer

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Ultralow-voltage, minimum-energy CMOS

IBM Journal of Research and Development - Advanced silicon technology
Self-Measurement of Combinatorial Circuit Delays in FPGAs

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Degradation in FPGAs: measurement and modelling

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Random variability modeling and its impact on scaled CMOS circuits

Journal of Computational Electronics
Limit study of energy & delay benefits of component-specific routing

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

Quantified Score

Hi-index	0.00

Visualization

Abstract

Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and type of process variation that exists in the FPGA. To obtain these delays, Timing Extraction measures, using only resources already available in the FPGA, the delay of a small subset of the total paths in the FPGA. We apply Timing Extraction to the Logic Array Block (LAB) on an Altera Cyclone III FPGA to obtain a view of the delay down to near individual LUT granularity, characterizing components with delays on the order of a few hundred picoseconds with a resolution of ±3.2 ps. This information reveals that the 65 nm process used has, on average, random variation of Ã/¼ = 4.0% with components having an average maximum spread of 83 ps. Timing extraction also shows that as VDD decreases from 1.2 V to 0.9 V in a Cyclone IV 60 nm FPGA, paths slow down and variation increases from Ã/¼ = 4.3% to Ã/¼ = 5.8%, a clear indication that lowering VDD magnifies the impact of random variation.