High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Line edge roughness (LER) reduction strategy for SOI waveguides fabrication
Microelectronic Engineering
Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch
Microelectronics Journal
Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch
Microelectronics Journal
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Efficient variation-aware statistical dynamic timing analysis for delay test applications
Proceedings of the Conference on Design, Automation and Test in Europe
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Random variations have been regarded as one of the major barriers on CMOS scaling. Compact models that physically capture these effects are crucial to bridge the process technology with design optimization. In this paper, 3-D atomistic simulations are performed to investigate fundamental variations in a scaled CMOS device, including random dopant fluctuation (RDF), line-edge roughness (LER), and oxide thickness fluctuation (OTF). By understanding the underlying physics and analyzing simulation results, compact models for random threshold (V th ) variations are developed. The models are scalable with device specifications, enabling quantitative analysis of circuit performance variability in future technology nodes. Using representative circuits, such as the inverter chain and SRAM cell, key insights are extracted on the trend of variability, as well as the implications on robust design.