Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Characterisation of FPGA Clock Variability
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Self-Measurement of Combinatorial Circuit Delays in FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Degradation in FPGAs: measurement and modelling
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
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Literature suggests that timing performance degradation in VLSI could be a major concern in future process technologies. FPGAs are well suited to cope with this challenge, due to their flexibility at design-, manufacture- and run-time. Existing timing measurement techniques allow for the measurement of delay while the circuit is not operating, and reliability techniques allow for the detection of faults as they occur in operating circuits. Neither allows for the health of an operating circuit to be measured. The ability to monitor the health of a system can provide an early warning of impending failure. This information will enable measures to reduce the impact of, or avoid altogether, the failure. A good indication of the degree of degradation in an operating circuit is the available timing slack in a combinatorial circuit path, between registers, while the circuit is operating at speed. This work proposes a new time delay measurement technique that does not interfere with the circuit's normal operation. This is achieved by sweeping the phase of a secondary clock signal, driving additional shadow registers. These are connected to each circuit node to be measured, typically those on the most critical paths. The technique is able to measure the timing slack available in the circuit-under-test, while it is performing its usual function. The technique is demonstrated using a 12-stage LUT chain, and on an 8-bit ripple-carry adder, implemented on an Altera Cyclone III FPGA. It is able to measure the timing slack with a best case resolution of 96ps. The additional circuitry has minimal overhead in terms of area, power consumption, and timing. The increase in circuit delay due to extra fan-out load was measured to be 0.25% in the first example circuit.