Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring
IEEE Transactions on Computers
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Reconfigurable Mesh-Connected Processor Arrays Using Row-Column Bypassing and Direct Replacement
ISPAN '00 Proceedings of the 2000 International Symposium on Parallel Architectures, Algorithms and Networks
Enhanced Cluster k-Ary n-Cube, A Fault-Tolerant Multiprocessor
IEEE Transactions on Computers
Simultaneous timing-driven placement and duplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Online fault tolerance for FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault tolerant placement and defect reconfiguration for nano-FPGAs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Degradation in FPGAs: measurement and modelling
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
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We address the problem of optimizing fault tolerance in FPGA architectures with high defect rates (such as nano-FPGAs) without significantly degrading performance. Our methods address fault tolerance during the placement and reconfiguration stages of FPGA programming. First, we provide several complexity results for both the fault reconfiguration and fault-tolerance placement problems. Then, we propose a placement algorithm which, in the presence of randomly generated faults, optimizes spare placement to maximize the probability that the FPGA can be reconfigured to meet a specified timing constraint. We also give heuristics for reconfiguration after faults have been detected. Despite the hardness results for both the placement and reconfiguration problems, we show our heuristics perform well in simulation (in one scenario, increasing the probability of successful reconfiguration by as much as 55% compared to a uniform spare placement).