Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
BIST-Based Diagnostics of FPGA Logic Blocks
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fault tolerant placement and defect reconfiguration for nano-FPGAs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An evaluation of a slice fault aware tool chain
Proceedings of the Conference on Design, Automation and Test in Europe
The survivability of design-specific spare placement in FPGA architectures with high defect rates
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Significant increases in chip yield can result if faulty logic cells and wiring in Field Programmable Gate Arrays (FPGAs) can be isolated from the remainder of the circuitry to retain a completely usable chip. Utilizing the principle of node-covering, a routing discipline has been developed that allows each logic cell in an FPGA to cover -- to be able to replace -- its neighbor in a row. An FPGA is factory-reconfigured such that a faulty cell is replaced by its cover, which in turn is replaced by its own cover, and so on until a spare cell in the row is reached. Since wiring channel area is a major portion of chip area in an FPGA, new techniques are also proposed for tolerating wiring faults. As with faulty logic cells, faulty wiring portions are replaced by adjacent ones, until eventually a spare wiring portion is reached. Compared to other techniques for fault tolerance in FPGAs, these methods are shown to provide significantly greater yield improvement.