Test and diagnosis of fault logic blocks in FPGAs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Universal Fault Diagnosis for Lookup Table FPGAs
IEEE Design & Test
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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As FPGA sizes and densities grow, their manufacturing yields decrease. This work looks toward reclaiming some of this lost yield. Several previous works have suggested fault aware CAD tools for intelligently routing around faults. In this work we evaluate such an approach quantitatively with respect to some standard benchmarks. We also quantify the trade-offs between performance and fault tolerance in such a method. Leveraging existing CAD tools, we show up to 30% of slices being faulty can be tolerated. Such approaches could potentially allow manufacturers to sell larger chips with manufacturing faults as smaller chips using a nomenclature that appropriately captures the reduction in logic resources.