Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Evaluation of FPGA resources for built-in self-test of programmable logic blocks
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
On Routability for FPGAs under Faulty Conditions
IEEE Transactions on Computers
Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Defect Tolerant SRAM Based FPGAs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Using ILA Testing for BIST in FPGAs
Proceedings of the IEEE International Test Conference on Test and Design Validity
Defect tolerance on the Teramac custom computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Design of Easily Testable Bit-Sliced Systems
IEEE Transactions on Computers
| Hi-index | 0.00 |
Abstract: Accurate diagnosis is an essential requirement inmany testing environments, since it is the basis for any repairor replacement strategy used for chip or system fault-tolerance.In this paper we present the first approach able todiagnose faulty programmable logic blocks (PLBs) in FieldProgrammable Gate Arrays (FPGAs) with maximal diagnosticresolution. Our approach is based on a new Built-In Self-Test(BIST) architecture for FPGAs and can accurately locateany single and most multiple faulty PLBs. An adaptive diagnosticstrategy provides identification of faulty PLBs with a7% increase in testing time over the complete detection test,and can also be used for manufacturing yield enhancement.We present results showing identification of faulty PLBs indefective ORCA chips.1