The survivability of design-specific spare placement in FPGA architectures with high defect rates
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
An advanced spare-connection scheme for k -out-of- n redundancy is proposed for constructing fault-tolerant ring- or to roidal mesh-connected arrays of processing nodes able to enhance emulation of binary hypercubes by using bypass networks. With this scheme, a component redundancy configuration for a base array with a fixed number of primary nodes, such as that for 8-node ring or 32-node to roidal mesh, can be constructed by using by-pass links with a segmented bus structure to selectively connect the primary nodes to a spare node in parallel. These by pass links are allocated to the primary no des by graph-node coloring with a minimum inter-node distance of three in order to use the bypass links as the hypercube connections as well as to attain strong fault tolerance for reconfiguring the base array with the primary network topology. An extended redundancy configuration for a large fault-tolerant array can be constructed by connecting the component configurations by using external switches of a hub type provided at the bus nodes of the bypass links. This configuration has a network topology of the parallel star-connections of sub-hypercubes whose diameter is smaller than that of the regular hypercube.