Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An analytic net weighting approach for performance optimization in circuit placement
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
Characterization and parameterized random generation of digital circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Optimality, scalability and stability study of partitioning and placement algorithms
Proceedings of the 2003 international symposium on Physical design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimality study of logic synthesis for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Eyecharts: constructive benchmarking of gate sizing heuristics
Proceedings of the 47th Design Automation Conference
Improving FPGA placement with dynamically adaptive stochastic tunneling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Construction of realistic gate sizing benchmarks with known optimal solutions
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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This work studies the optimality and stability of timing-drivenplacement algorithms. The contributions of this work include twoparts: 1) We develop an algorithm for generating synthetic examples with known optimal delay for timing driven placement(T-PEKO). The examples generated by our algorithm can closelymatch the characteristics of real circuits. 2) Using these syntheticexamples with known optimal solutions, we studied the optimalityof several timing-driven placement algorithms for FPGAs by comparing their solutions with the optimal solutions, and their stability by varying the number of longest paths in the examples. Our study shows that with a single longest path, the delay produced by these algorithms is from 10% to 18% longer than the optima on the average, and from 34% to 53% longer in the worst case. Furthermore, their solution quality deteriorates as the number of longest paths increases. For examples with more than 5 longest paths, their delay is from 23% to 35% longer than the optima on the average, and is from 41% to 48% longer in the worst case.