Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems
SP '07 Proceedings of the 2007 IEEE Symposium on Security and Privacy
Trojan Detection using IC Fingerprinting
SP '07 Proceedings of the 2007 IEEE Symposium on Security and Privacy
Designing and implementing malicious hardware
LEET'08 Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats
At-speed delay characterization for IC authentication and Trojan Horse detection
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Experiences in Hardware Trojan design and implementation
HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
Security against hardware Trojan through a novel application of design obfuscation
Proceedings of the 2009 International Conference on Computer-Aided Design
Consistency-based characterization for IC Trojan detection
Proceedings of the 2009 International Conference on Computer-Aided Design
A Survey of Hardware Trojan Taxonomy and Detection
IEEE Design & Test
Gate-level characterization: foundations and hardware security applications
Proceedings of the 47th Design Automation Conference
Overcoming an Untrusted Computing Base: Detecting and Removing Malicious Hardware Automatically
SP '10 Proceedings of the 2010 IEEE Symposium on Security and Privacy
Tamper Evident Microprocessors
SP '10 Proceedings of the 2010 IEEE Symposium on Security and Privacy
Self-referencing: a scalable side-channel approach for hardware Trojan detection
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
SP '11 Proceedings of the 2011 IEEE Symposium on Security and Privacy
Defeating UCI: Building Stealthy and Malicious Hardware
SP '11 Proceedings of the 2011 IEEE Symposium on Security and Privacy
Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry
Proceedings of the 49th Annual Design Automation Conference
IEEE Spectrum
Breakthrough silicon scanning discovers backdoor in military chip
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
| Hi-index | 0.00 |
Hardware Trojans (HTs) implemented by adversaries serve as backdoors to subvert or augment the normal operation of infected devices, which may lead to functionality changes, sensitive information leakages, or Denial of Service attacks. To tackle such threats, this paper proposes a novel verification technique for hardware trust, namely VeriTrust, which facilitates to detect HTs inserted at design stage. Based on the observation that HTs are usually activated by dedicated trigger inputs that are not sensitized with verification test cases, VeriTrust automatically identifies such potential HT trigger inputs by examining verification corners. The key difference between VeriTrust and existing HT detection techniques is that VeriTrust is insensitive to the implementation style of HTs. Experimental results show that VeriTrust is able to detect all HTs evaluated in this paper (constructed based on various HT design methodologies shown in the literature) at the cost of moderate extra verification time, which is not possible with existing solutions.