Handbook of Applied Cryptography
Handbook of Applied Cryptography
Reuse Techniques for VLSI Design
Reuse Techniques for VLSI Design
Virtual Components Design and Reuse
Virtual Components Design and Reuse
A Public-Key Watermarking Technique for IP Designs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection
ICCTA '07 Proceedings of the International Conference on Computing: Theory and Applications
Trojan Detection using IC Fingerprinting
SP '07 Proceedings of the 2007 IEEE Symposium on Security and Privacy
IPP@HDL: efficient intellectual property protection scheme for IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Remote activation of ICs for piracy prevention and digital right management
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
Protecting bus-based hardware IP by secret sharing
Proceedings of the 45th annual Design Automation Conference
Encoding of Floorplans through Deterministic Perturbation
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Techniques for Design and Implementation of Secure Reconfigurable PUFs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An Efficient and Reliable Watermarking System for IP Protection
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Modern VLSI Design: IP-Based Design
Modern VLSI Design: IP-Based Design
At-speed delay characterization for IC authentication and Trojan Horse detection
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
First-Order Side-Channel Attacks on the Permutation Tables Countermeasure
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Hardware authentication leveraging performance limits in detailed simulations and emulations
Proceedings of the 46th Annual Design Automation Conference
Hardware Trojan horse detection using gate-level characterization
Proceedings of the 46th Annual Design Automation Conference
Information hiding for trusted system design
Proceedings of the 46th Annual Design Automation Conference
Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design
Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
Integration, the VLSI Journal
HARPOON: an obfuscation-based SoC design methodology for hardware protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Unified Approach for IP Protection across Design Phases in a Packaged Chip
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Gate-level characterization: foundations and hardware security applications
Proceedings of the 47th Design Automation Conference
Synthesis of trustable ICs using untrusted CAD tools
Proceedings of the 47th Design Automation Conference
Towards Hardware-Intrinsic Security: Foundations and Practice
Towards Hardware-Intrinsic Security: Foundations and Practice
Constraint-based watermarking techniques for design IP protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fingerprinting techniques for field-programmable gate array intellectual property protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Designing high-performance fuzzy controllers combining IP cores and soft processors
Advances in Fuzzy Systems - Special issue on High Performance Fuzzy Systems for Real World Problems
RFID based access control protection scheme for SRAM FPGA IP cores
Microprocessors & Microsystems
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Increased design complexity, shrinking design cycle, and low cost--this three-dimensional demandmandates advent of system-onchip (SoC) methodology in semiconductor industry. The key concept of SoC is reuse of the intellectual property (IP) cores. Reuse of IPs on SoC increases the risk of misappropriation of IPs due to introduction of several new attacks and involvement of various parties as adversaries. Existing literature has huge number of proposals for IP protection (IPP) techniques to be incorporated in the IP design flow as well as in the SoC design methodology. However, these are quite scattered, limited in possibilities in multithreat environment, and sometimes mutually conflicting. Existing works need critical survey, proper categorization, and summarization to focus on the inherent tradeoff, existing security holes, and new research directions. This paper discusses the IP-based SoC design flow to highlight the exact locations and the nature of infringements in the flow, identifies the adversaries, categorizes these infringements, and applies strategic analysis on the effectiveness of the existing IPP techniques for these categories of infringements. It also clearly highlights recent challenges and new opportunities in this emerging field of research.